The present invention generally relates to semiconductor fabrication, and in particular to systems and methods for monitoring sheet resistivity of silicides during rapid thermal annealing (RTA) and for controlling RTA based on such monitoring.
In the semiconductor industry, there is a continuing trend toward manufacturing integrated circuits with a greater number of layers and with higher device densities. To achieve these greater number of layers and higher densities there have been, and continue to be, efforts towards reducing the thickness of layers, improving the uniformity of layers, reducing the thickness of devices and scaling down device dimensions (e.g., at sub micron levels) on semiconductor wafers. In order to accomplish higher device packing densities, thinner layers and more uniform layers with more precisely controlled conductivity and/or resistivity are required. This can include the thickness of gate oxide materials, (e.g., silicon oxide, silicon nitride, silicon oxynitride), thin films, and other layers.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit can be formed on a single wafer. Generally, the process involves creating several layers on and in a substrate that ultimately forms the complete integrated circuit. This layering process can create electrically active regions in and on the semiconductor wafer surface. Insulation and conductivity between such electrically active regions can be important to reliable operation of such integrated circuits. Thus, controlling the thickness, uniformity and conducting and/or insulating properties of layers created during the layering process can be important to the reliable operation of such integrated circuits.
Rapid thermal annealing (RTA) can be employed in fabricating one or more layers on a semiconductor. RTA is known to those skilled in the art, and thus for the sake of brevity is only briefly discussed herein. RTA is one form of rapid thermal processing (RTP) wherein a wafer is heated to a specific, usually high temperature for short periods of time. There are at least two forms of RTA commonly employed in semiconductor manufacturing. Adiabatic annealing refers to RTA where the heating time is less than 10xe2x88x927 seconds. When adiabatic annealing is employed, typically only a thin surface on a wafer is affected. Adiabatic annealing can be performed by a high energy laser pulse that heats and thus melts the desired material. Such high energy laser pulses may be focused on all and/or a part of a wafer to localize the RTA affects. Isothermal annealing involves heating processes longer than adiabatic annealing. Adiabatic annealing can be performed by heating associated with tungsten/halogen lamps and/or graphite resistive strips, for example, to heat a wafer from one or both sides, or to selectively heat a portion of a wafer.
One purpose of RTA can be to repair damage (e.g., lattice damage) caused during doping. Such damage can occur because implanting dopant atoms into a semiconductor can displace many atoms for each implanted ion. Electrical behavior after implantation can be dominated by deep-level electron and hole traps, which can capture carriers and make sheet resistivity high. Annealing can be employed to repair such lattice damage and to place dopant atoms on substitutional sites where they will be electrically active and facilitate producing desired conducting and/or insulating properties, as measured by sheet resistivity, for example.
Sheet resistivity of a semiconductor or thin metal film is the ratio of the potential gradient (electric field) parallel with the current to the product of the current density and thickness. RTA can affect sheet resistivity by, for example, affecting the thickness, uniformity, composition and lattice configuration of semiconductor materials. Sheet resistivity can be important to the proper operation of a semiconductor, and thus, producing wafers with sheet resistivity within a desired range is important.
Difficulties in forming a layer, with precise thickness and/or uniformity, and thus with precise resistivity, have limited the effectiveness and/or properties of semiconductor devices manufactured by conventional techniques. The more precisely a layer can be formed, the more precisely critical dimensions may be achieved, with a corresponding increase in semiconductor performance and reliability. Conventionally, due to non-uniform layer formation and inaccurate layer formation monitoring techniques, an undesired sheet resistivity may be encountered, thereby comprising semiconductor performance and reliability.
Conventional techniques for analyzing RTA results in situ (e.g, scanning electron microscopy), if employed, are not a direct measurement of the desired property, but rather are an indirect method for determining whether a desired sheet resistivity will be produced. Thus, results generated from such conventional techniques may not be as precise as desired, resulting in layers with a sheet resistivity not within a desired range.
Difficulties in precisely forming a layer with a precise sheet resistivity can occur for reasons including, but not limited to, employing indirect measurement methods, variations within a wafer, variations between wafers in a lot, variations between wafer lots, wear and tear on RTA apparatus, local variations in a wafer caused by RTA, optical interference caused, for example, by etchings on a wafer, and miscalculations of RTA times and/or temperatures. Thus, a system for more precisely forming layers with sheet resistivity within a more precise range is still required.
This section presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is not intended to identify key/critical elements of the invention nor is it intended to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides for a system that facilitates monitoring sheet resistivity of a layer on a wafer and for controlling rapid thermal annealing (RTA) of the layer. The system includes RTA components that perform RTA on the layer and one or more sheet resistivity analyzing components that analyze the sheet resistivity of one or more portions of the layer upon which the RTA components perform the RTA. The system further includes a feedback generator that accepts sheet resistivity data from the analyzing components and produces feedback information that can be employed to control the one or more RTA components.
One or more RTA heating components can be arranged to correspond to a particular wafer portion. Each RTA heating component may be responsible for heating a portion of a layer during RTA. The RTA heating components are selectively driven by the system to heat one or more particular wafer portions during RTA at a desired temperature for a desired time. The progress and/or acceptability of the annealing is monitored by the system by comparing sheet resistivity measured by electrical methods to a desired sheet resistivity. Different wafers and even different portions of a wafer may benefit from different sheet resistivity. By monitoring sheet resistivity at one or more wafer portions, the present invention enables selective RTA to achieve desired sheet resistivity. As a result, more optimal layer formation is achieved, which in turn improves semiconductor device manufacturing.
Another aspect of the present invention provides a system that facilitates monitoring sheet resistivity of a layer on a wafer by electrical methods and for controlling rapid thermal annealing (RTA) of the layer. The system includes a data store that can be utilized to facilitate generating feedback information that can be employed to control RTA. The data store can also be utilized to facilitate machine learning that can be employed to perform RTA control.
Yet another aspect of the present invention provides a system that facilitates monitoring sheet resistivity of a layer on a wafer by electrical methods and for controlling rapid thermal annealing (RTA) of the layer. The system includes a monitoring application that can be employed to analyze feedback information generated by a feedback generator and/or to analyze data stored in a data store. The analyses performed by the monitoring application can be employed to generate information including, but not limited to, productivity reports, error reports and maintenance schedules.
Another aspect of the present invention provides a method for regulating layer formation. The method includes partitioning a layer into portions, performing rapid thermal annealing on a portion and measuring sheet resistivity in the portions using electrical methods. Sheet resistivity measurements are analyzed to determine whether an acceptable sheet resistivity exists at the portions and the analysis is employed to generate feedback information that can be sent to RTA components and employed to control RTA components corresponding to layer portions.
Still yet another aspect of the present invention provides a system for regulating layer formation on a silicide wafer including first sensing means for sensing conducting properties of a layer; second sensing means sensing insulating properties of a layer; rapid thermal processing means for heating a layer; and controlling means for selectively controlling the rapid thermal processing means so as to regulate layer formation.
To the accomplishment of the foregoing and related ends, the invention, then, comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.